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TM
MP8040
High Current Integrated Half Bridge + Driver
The Future of Analog IC Technology
TM
DESCRIPTION
The MP8040 is a general purpose, high frequency half bridge power driver capable of driving a 9A load. The devices integrates both top and bottom N-Channel MOSFET power switches and is fully protected from both sourcing and sinking current by a preset cycle-by-cycle current limit. It has a wide input voltage range from 7.5V to 25V. The MP8040 features a low-current shutdown mode, input under-voltage protection, thermal shutdown, and fault flag signal output. It interfaces with standard logic signals and is available in a small 8-pin SOIC with exposed pad package.
FEATURES
* * * * * * * * * * * * * * 9A Peak Current Output 4.25A Continuous Current Output Up to 1.2MHz Switching Frequency Protected Integrated Power 100m Switches All Switches Current Limited Integrated Under-Voltage Protection Integrated Thermal Protection 2.5A Standby Mode True 2-Quadrant Operation Sources and Sinks Current Fault Indicator Output Class D Audio Driver o 25W/4/10% Output Power Single Ended o 70W/4/10% Output Power Full Bridge Full or Half Bridge DC-DC Switching Regulator Motor Driver
APPLICATIONS
EVALUATION BOARD REFERENCE
Board Number EV0041 Dimensions 3.5"X x 3.5"Y x 1.2"Z
"MPS" and "The Future of Analog IC Technology" are Trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VSP
2 7 SP DRV +
FAULT ENABLE PWM SIGNAL
8 6 1
FLT SHDN PWM
MP8040
BS SW 5 3
47nF VOUT
GND 4
MP8040_TAC_S01
MP8040 Rev. 1.5 5/3/2005
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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MP8040 - HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER
PACKAGE REFERENCE
TOP VIEW
PWM SP SW GND 1 2 3 4 8 7 6 5 FLT DRV SHDN BS
ABSOLUTE MAXIMUM RATINGS (1)
SP Supply Voltage (VSP).............................. 28V SW Pin Voltage .............................. -0.3V to VSP SW to BS ....................................... -0.3V to +6V Voltage at All Other Pins ............... -0.3V to +6V Storage Temperature .............. -55C to +150C
Recommended Operating Conditions
(2)
EXPOSED PAD ON BACKSIDE CONNECT TO PIN 4
MP8040_PD01-SOIC8N
SP Supply Voltage (VSP).................. 7.5V to 24V Peak Output Current...................... 9A Maximum Operating Temperature ............. -40C to +85C
Thermal Resistance
Temperature -40C to +85C
(3)
SOIC8N .................................. 50 ....... 8.... C/W
Part Number* MP8040DN * Package SOIC8N (Exposed Pad)
Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1" square of 1 oz copper.
JA
JC
For Tape & Reel, add suffix -Z (eg. MP8040DN-Z) For Lead Free, add suffix -LF (eg. MP8040DN-LF-Z)
ELECTRICAL CHARACTERISTICS
VSP = 12V, VSHDN = 0V, TA = +25C, unless otherwise noted.
Parameter SP Operating Current SP Shutdown Current SHDN, SP Threshold Low SHDN, SP Threshold High SHDN, SP Input Bias Current SW On Resistance SW Current Limit
(4)
Symbol Condition VSHDN = 2V
Min
Typ 1.5 2.5
Max 2.5 10 1
2 VSP = 7.5V, High-Side and Low-Side VPWM = 5, (Sinking) VPWM = 0, (Sourcing) VPWM = 0 to 2V, 50% Duty Cycle VSP = 7.5V, VPWM = 2V, CSW 100nF, fSW = 3.3KHz VPWM = 0 to 5V VPWM = 0 to 2V, High or Low Pulse VPWM = 0 to 5V VPWM = 5 to 0V TJ Rising, Hysteresis = 20C 1 0.1 9 9 1.2 99.5 20 200 70 70 160
SW Switching Frequency SW Maximum Duty Cycle
(5)
Units mA A V V A A A MHz % ns ns ns ns C
SW Rise/Fall Time PWM Pulse Width PWM to SW Delay Time Rising PWM to SW Delay Time Falling Thermal Shutdown Temperature (4)
Notes: 4) Guaranteed by design; not production tested. 5) SW drives low for 1.5s every 300s to charge the BS to SW capacitor.
MP8040 Rev. 1.5 5/3/2005
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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MP8040 - HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS
Circuit of Figure 4, TA = +25C, unless otherwise noted.
Delay Time SW Falling (VSP=8V)
Delay Time SW Rising (VSP=8V)
VPWM 2V/div.
VPWM 2V/div.
VSW 5V/div. 10.0ns/div.
MP8040-TPC01
VSW 5V/div. 10.0ns/div.
MP8040-TPC02
Delay Time SW Falling (VSP=25V)
VPWM 2V/div.
Delay Time SW Rising (VSP=25V)
VPWM 2V/div.
VSW 10V/div.
VSW 10V/div.
10.0ns/div.
MP8040-TPC03
10.0ns/div.
MP8040-TPC04
20
THD+N (%)
2 1 0.2 0.1 0.02 0.01 200m
12 10 20 OUTPUT POWER (W)
100
MP8040-TPC05
MP8040 Rev. 1.5 5/3/2005
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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MP8040 - HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER
PIN FUNCTIONS
Pin # 1 2 3 4 5 6 7 8 Name PWM SP SW GND BS SHDN DRV FLT Description Driver Logic Input. Drive PWM with the signal that controls the MP8040 output. Drive PWM high to turn on the high-side switch; drive PWM low to turn on the low-side switch. Power Supply Input. Connect SP to the positive side of the input power supply. Bypass SP to GND as close to the IC as possible. Switched Output. SW is the power output of the MP8040. Connect the output LC filter to SW. SW is valid approximately 100s after SP goes high. Ground. (Note: Connect the exposed pad on the bottom side to Pin 4). Bootstrap Supply. BS powers the high-side gate of the MP8040. Connect a 0.1F or greater capacitor between BS and SW. Shutdown Input. SHDN enables/disables the MP8040. Drive SHDN low to turn on the MP8040, drive it high to turn it off. If not used, connect SHDN to GND. Gate Drive Supply Bypass. The voltage at DRV is supplied from an internal regulator from SP. DRV powers the internal circuitry and internal MOSFET gate drives. Bypass DRV to GND with a 0.1F to 10F capacitor. Fault Output. Active-low, open drain. A low output at FLT indicates that the MP8040 has detected a fault and has shutdown. Connect FLT to DRV through a 100k resistor.
OPERATION
The MP8040 is a general purpose, power driver. It takes a logic input and drives a half bridge comprised of 0.1 high-side and low-side N-Channel MOSFET switches. It operates at frequencies up to 1.2MHz, can accept a DC supply voltage as high as 25V, and produce peak output current as high as 9A.
5 BS DBS BS UVLO
INTERNAL 5V REG. CURRENT LIMIT & FEEDBACK THERMAL SHUTDOWN UVLO
2 SP
DRV
7 HI DRIVE
PWM
1
LOGIC
3 SW
FLT SHDN
8
LO DRIVE
6
4 GND
MP8040_F02
Figure 1--Function Block Diagram
MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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MP8040 - HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER
SW Output The SW output drives the load. It is controlled by the logic input signal at PWM. When the signal at PWM is high (above 2V), the high-side switch is turned on. When the signal at PWM is low (less than 0.4V), the low-side switch is turned on. The MP8040 uses internal N-Channel MOSFETs for both the high-side and low-side switches. The high-side MOSFET gate drive is powered from the voltage between SW and BS, allowing BS to rise above the SP input voltage to power the high-side MOSFET. To do this a bootstrap capacitor is connected between SW and BS. When the low-side switch is on, the capacitor is internally charged from the voltage at DRV, which is also internally generated. There is a dead time region (typically 40ns) where both the upper and lower switches are off (see Figure 2). Both the high-side and low-side switches have internal current limits to prevent failure due to excessive load current. Once the current limit is reached, both output switches are turned off and the fault output is asserted (driven low). Shutdown The MP8040 includes a 2.5A shutdown mode. When SHDN is high, both output switches are turned off and the input current drops to 2.5A. When the MP8040 is shutdown, the internally generated voltage at DRV drops to 0V, and the fault output (FLT) is asserted (driven low). If the shutdown mode is not used, connect SHDN directly to GND. Fault Output The MP8040 includes a fault indicator output (FLT). This is an active-low open drain output. The MP8040 detects faults due to over-current (>9A), over-temperature (>160C), undervoltage at SP (<6.5V), or if the part is disabled. Connect FLT to DRV or to an external voltage up to 6V through a 27k or greater resistor. When any of the 3 fault conditions are detected, both output switches are turned off and the SW output is high-impedance.
Thermal Shutdown The MP8040 includes a thermal overload protection circuit. If the die temperature rises above 160C, the output switches are turned off and the fault output is asserted. Once the thermal overload circuit is tripped, the die temperature must drop below 140C before automatically restarting.
VSP
2 SP
MP8040
SW GND 4
3
SW VSP
3/4 VSP
1/2 VSP
1/4 VSP TIME DT (RISE) DT (FALL)
DEAD TIME RISING = 20ns DEAD TIME FALLING = 40ns
MP8040_F01
Figure 2--Dead Time
MP8040 Rev. 1.5 5/3/2005
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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MP8040 - HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER
TYPICAL APPLICATION CIRCUITS
VSP
VSP
2 7 DRV SP BS 8 6 1 5
+
7 DRV
2 SP BS 8 5 +
FLT
FAULT ENABLE PWM SIGNAL
FAULT
MP8040
SW 3
FLT
MP8040
+
SW 3
PWM CONTROLLER
6 ENABLE 1 PWM SIGNAL PWM GND 4 SHDN
VOUT
SHDN PWM GND 4
MP8040_F03
MP8040_F04
Figure 3--Single Ended Audio Amplifier
Figure 4--General Purpose DC to DC Converter
VSP
VSP
2 7 DRV SP BS 8 6 SHDN 1 PWM GND 4 SW 5
2
+
+
7
DRV
SP BS 5
FAULT ENABLE DIGITAL AUDIO SIGNAL
FLT
MP8040
3
FAULT ENABLE PWM SIGNAL
8 6
FLT
MP8040
SW 3
SHDN 1 PWM GND 4
VSP
2 7 DRV SP BS 8 6 SHDN 1 PWM GND 4 SW 5
VSP
+
M
2 7 DRV SP BS 8 6 SHDN 1 PWM GND 4
MP8040_F06
+
FAULT ENABLE
FLT
MP8040
3
5
FAULT ENABLE
MP8040_F05
FLT
MP8040
SW 3
Figure 5--80W Full Bridge Audio Amplifier
Figure 6--Full Bridge Motor Driver
MP8040 Rev. 1.5 5/3/2005
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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MP8040 - HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER
VSP
2 7 DRV SP BS 8 5
+
I/O
FLT
FAULT I2C
MP8040
SW 3
MICRO CONTROLLER
6 SHDN 1 PWM GND 4
I/O
ON/OFF
PWM ADC1 ADC2 ADC3
MP8040_F07
Figure 7--CCFL Driver Circuit
MP8040 Rev. 1.5 5/3/2005
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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MP8040 - HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER
PACKAGE INFORMATION
SOIC8N (EXPOSED PAD)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.
MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2005 MPS. All Rights Reserved.
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